The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 23, 2009
Filed:
Nov. 25, 2003
Frank William Brice, Jr., Hurley, NY (US);
Richard K. Errickson, Poughkeepsie, NY (US);
Mark S. Farrell, Pleasant Valley, NY (US);
Charles W. Gainey, Jr., Poughkeepsie, NY (US);
Thomas A. Gregg, Highland, NY (US);
Carol B. Hernandez, Poughkeepsie, NY (US);
Damian L. Osisek, Vestal, NY (US);
Donald W. Schmidt, Stone Ridge, NY (US);
Frank William Brice, Jr., Hurley, NY (US);
Richard K. Errickson, Poughkeepsie, NY (US);
Mark S. Farrell, Pleasant Valley, NY (US);
Charles W. Gainey, Jr., Poughkeepsie, NY (US);
Thomas A. Gregg, Highland, NY (US);
Carol B. Hernandez, Poughkeepsie, NY (US);
Damian L. Osisek, Vestal, NY (US);
Donald W. Schmidt, Stone Ridge, NY (US);
International Business Machines, Armonk, NY (US);
Abstract
A method of performing memory mapped input output operations to an alternate address space comprising: establishing a first instruction directed to a first memory mapped input output alternate address space associated with an adapter to store data in accordance with a definition of a z/Architecture; establishing a second instruction directed to the first memory mapped input output alternate address space associated with an adapter to load data in accordance with a definition of a z/Architecture; allocating at least one of a real resource and a virtual resource associated with the first alternate address space to a process; ensuring that the selected process corresponds with the process to which the resource is allocated. The process issues at least one of the first instruction and the second instruction and thereby causes execution of at least one of the store and load with the first alternate address space.