The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2009

Filed:

Oct. 02, 2006
Applicants:

Tatsuya Tetsukawa, Osaka, JP;

Minoru Okamoto, Osaka, JP;

Shinichi Marui, Osaka, JP;

Inventors:

Tatsuya Tetsukawa, Osaka, JP;

Minoru Okamoto, Osaka, JP;

Shinichi Marui, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
Abstract

A plurality of logic element groups LEGto LEGrespectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEGand LEG, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element. The logic element groups LEGto LEGare therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.


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