The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7550389 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 23, 2009

Filed:

Jun. 11, 2008
Applicants:

Chang Jun Yoo, Gyeonggi-do, KR;

GA Young Ha, Gyeonggi-do, KR;

Inventors:

Chang Jun Yoo, Gyeonggi-do, KR;

Ga Young Ha, Gyeonggi-do, KR;

Assignee:

Hynix Semiconductor Inc., Kyoungki-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
Abstract

A dual damascene method of forming a metal line of a semiconductor device includes the procedures of: forming, partially annealing, etching, and cleaning. The forming procedure includes forming an SOD (spin-on dielectric) layer on an insulation layer having a contact hole to fill the contact hole. The partially annealing procedure includes annealing the SOD layer to selectively bake portions of the SOD layer which are filled in an upper portion of the contact hole and placed on the insulation layer. The etching procedure includes etching the baked portions of the SOD layer and a portion of the insulation layer to define a trench. The cleaning procedure includes cleaning the resultant structure of the trench and to remove substantially all of the unbaked portion of the SOD layer which remains in a lower portion of the contact hole.


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Yoo, Chang. (2009). Dual damascene method of forming a metal line of semiconductor device (U.S. Patent No. 7550389). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7550389

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