Dynamic adjusting circuit for basic clock signal of front-side bus and method thereof

Abstract

By adjusting a scale factor of a phase locked loop in computers for generating a basic clock signal of a front-side bus, the frequency of the basic clock signal is modulated when the central processing unit of computers operates. By a bridge unit of the present invention, a selecting signal is received so as to output a corresponding adjustment signal to a check unit and then the check unit checks the adjustment signal for outputting a checking signal to a scale parameter adjustment unit. According to the checking signal, the scale parameter adjustment unit adjusts a first scale parameter of the scale factor that the phase locked loop uses now and outputs this parameter to the phase locked loop. Thus after receiving a fixed clock signal for generating the basic clock signal, the phase locked loop generates the basic clock signal of the front-side bus in accordance with the adjusted first scale parameter and further the frequency of the basic clock signal is adjusted.