The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2009
Filed:
Sep. 12, 2005
David Baker, Chapel Hill, NC (US);
Christopher Basoglu, Bothell, WA (US);
Benjamin Cutler, Seattle, WA (US);
Gregorio Gervasio, Sunnyvale, CA (US);
Woobin Lee, Lynnwood, WA (US);
Yatin Mundkur, Sunnyvale, CA (US);
Toru Nojiri, Tokyo, JP;
John O'donnell, Seattle, WA (US);
John Poole, Legal Representative, Salem, OR (US);
Ashok Raman, San Jose, CA (US);
Eric Rehm, Bainbridge Island, WA (US);
Radhika Thekkath, Palo Alto, CA (US);
David Baker, Chapel Hill, NC (US);
Christopher Basoglu, Bothell, WA (US);
Benjamin Cutler, Seattle, WA (US);
Gregorio Gervasio, Sunnyvale, CA (US);
Woobin Lee, Lynnwood, WA (US);
Yatin Mundkur, Sunnyvale, CA (US);
Toru Nojiri, Tokyo, JP;
John O'Donnell, Seattle, WA (US);
John Poole, legal representative, Salem, OR (US);
Ashok Raman, San Jose, CA (US);
Eric Rehm, Bainbridge Island, WA (US);
Radhika Thekkath, Palo Alto, CA (US);
Hitachi, Ltd., , JP;
Equator Technologies, Inc., Campbell, CA (US);
Abstract
In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.