Memory device for early stabilizing power level after deep power down mode exit

Abstract

A memory device for early stabilization and rapid increase of a power level after deep power down exit includes a deep power down exit pulse generator, a deep power down exit mode signal generator, a current driving unit, a controller and a voltage generator. The deep power down exit pulse generator generates a deep power down exit pulse signal having a predetermined pulse width in response to a deep power down command. The deep power down exit mode signal generator generates a deep power down exit mode bias signal in response to the deep power down exit pulse signal. The current driving unit generates a deep power down exit mode reference voltage in response to the deep power down exit mode bias signal and a reference signal. The controller generates an enable signal in response to the deep power down exit mode bias signal or an active command. The voltage generator compares the deep power down exit mode reference voltage to an internal power supply voltage in response to the enable signal and outputs the internal power supply voltage. The memory device previously generates the internal power supply voltage, which is used in the active mode, in a deep power down exit mode before an active command is applied to the memory device, and thus a power-up ensuring time after deep power down mode exit can be reduced.