The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2009

Filed:

Jul. 13, 2007
Applicant:

Douglas R. Frey, Bethlehem, PA (US);

Inventor:

Douglas R. Frey, Bethlehem, PA (US);

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/16 (2006.01); H03L 7/18 (2006.01);
U.S. Cl.
CPC ...
Abstract

A phase-locked loop (PLL) achieves initial lock using a course fractional-N divider driving a binary phase detector. Once frequency lock is achieved, this divider may be turned off, while an adaptive phase detector takes over control of the PLL front end. The adaptive phase detector (APD) receives input directly from the VCO and the reference clock, deriving digital control signals and a precision phase detector output. The APD operates at the update rate, generating a digital delta sigma modulator (DSM) data stream output at the update rate. The APD automatically locks to a digitally generated ramp corresponding to an expected difference between the VCO output and the reference clock, while adaptively correcting for DC errors and ramp cancellation errors.


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