The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2009
Filed:
Jul. 14, 2006
Ravindraraj Ramaraju, Round Rock, TX (US);
Ambica Ashok, Austin, TX (US);
Cody B. Croxton, Austin, TX (US);
Peter M. Ippolito, Austin, TX (US);
Prashant U. Kenkare, Austin, TX (US);
Ravindraraj Ramaraju, Round Rock, TX (US);
Ambica Ashok, Austin, TX (US);
Cody B. Croxton, Austin, TX (US);
Peter M. Ippolito, Austin, TX (US);
Prashant U. Kenkare, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
The present invention provides a latch circuit that is operable to generate a pulse from first and second clock signals to allow gates in a datapath to propagate data with minimal latency. The first clock signal is a version of the system clock and the second control signal is a time-shifted, inverted version of the system clock signal. Each of the individual latches in a datapath comprises data propagation logic. In one embodiment of the invention, the data propagation logic uses the first and second clock signals to generate an 'implicit' pulse. In another embodiment of the invention, the data propagation logic uses the first and second clock signals to generate an 'explicit' pulse. The implicit and explicit pulses are used to control the transmission gate of the latch to provide propagation of data through the latch with minimal latency.