The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 16, 2009
Filed:
Oct. 04, 2007
Pradyumna Kumar Swain, Princeton, NJ (US);
David Arthur Furst, Princeton, NJ (US);
Mahalingam Bhaskaran, Lawrenceville, NJ (US);
Pradyumna Kumar Swain, Princeton, NJ (US);
David Arthur Furst, Princeton, NJ (US);
Mahalingam Bhaskaran, Lawrenceville, NJ (US);
Sarnoff Corporation, Princeton, NJ (US);
Abstract
A method for fabricating CCD imaging structures is disclosed, comprising the steps of providing a silicon substrate; growing a dielectric layer substantially overlying the silicon substrate; depositing a first layer of polysilicon substantially overlaying the dielectric layer; removing at least a portion of the first layer of polysilicon to form a plurality of polysilicon gates and first predetermined inter-gate gaps, each of plurality of the polysilicon gates having a predetermined line width; depositing a second layer of polysilicon of a predetermined thickness substantially overlaying the plurality of polysilicon gates and the first predetermined inter-gate gaps; removing at least a portion of the second layer of polysilicon from between gates of the plurality of polysilicon gates to define a plurality of non-overlapping polysilicon gates and second predetermined inter-gate gaps that expose the dielectric layer, the second predetermined inter-gate gaps being smaller than the first predetermined inter-gate gaps.