The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2009

Filed:

Mar. 10, 2003
Applicants:

Glenn Henry, Austin, TX (US);

Rodney Hooker, Austin, TX (US);

Terry Parks, Austin, TX (US);

Inventors:

Glenn Henry, Austin, TX (US);

Rodney Hooker, Austin, TX (US);

Terry Parks, Austin, TX (US);

Assignee:

IP-First, LLC, Fremont, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/00 (2006.01); G06F 13/24 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of interrupts at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has and extended prefix and an extended prefix tag. The extended prefix specifies that interrupt processing be suppressed until execution of the extended instruction is completed, where the extended instruction prescribes an operation to be performed according to an existing instruction set. The extended prefix tag is an otherwise architecturally specified opcode within an existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and completes execution of the corresponding micro instructions prior to processing a pending interrupt.


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