The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2009
Filed:
Apr. 27, 2007
Jente B. Kuang, Austin, TX (US);
Jerry C. Kao, Ann Arbor, MI (US);
Hung Cai Ngo, Austin, TX (US);
Kevin J. Nowka, Georgetown, TX (US);
Jente B. Kuang, Austin, TX (US);
Jerry C. Kao, Ann Arbor, MI (US);
Hung Cai Ngo, Austin, TX (US);
Kevin J. Nowka, Georgetown, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.