Clock distribution for specialized processing block in programmable logic device

Abstract

Clocks are distributed efficiently to regions of a specialized processing block in a PLD. Multiple clocks are selected from a larger universe of clocks and distributed to the specialized processing block, but the choices of clocks at the individual functional regions, or stages of functional regions, are less than fully flexible. In some cases, an entire region may use one clock. In another case, portions of a stage within a region that previously had been able to select individual clocks must use one clock for the entire stage. In another case, only a subset of the selected clocks is available for a particular region, but that subset is flexibly distributable within the region. In another case, a clock may be selectable for each stage of each functional region directly from the larger universe of available clocks, avoiding the need for circuitry to select the multiple clocks from the larger universe.