The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 09, 2009
Filed:
Jun. 04, 2005
Yongli Huang, San Jose, CA (US);
Xuefeng Zhuang, Stanford, CA (US);
Butrus T. Khuri-yakub, Palo Alto, CA (US);
Ching-hsiang Cheng, Menlo Park, CA (US);
Arif S. Ergun, Mountain View, CA (US);
Yongli Huang, San Jose, CA (US);
Xuefeng Zhuang, Stanford, CA (US);
Butrus T. Khuri-Yakub, Palo Alto, CA (US);
Ching-Hsiang Cheng, Menlo Park, CA (US);
Arif S. Ergun, Mountain View, CA (US);
The Board of Trustees of the Leland Stanford Junior University, Palo Alto, CA (US);
Abstract
The embodiments of the present invention provide a CMUT array and method of fabricating the same. The CMUT array has CMUT elements individually or respectively addressable from a backside of a substrate on which the CMUT array is fabricated. In one embodiment, a CMUT array is formed on a front side of a very high conductivity silicon substrate. Through wafer trenches are etched into the substrate from the backside of the substrate to electrically isolate individual CMUT elements formed on the front side of the substrate. Electrodes are formed on the backside of the substrate to individually address the CMUT elements through the substrate.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile