The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 09, 2009

Filed:

Mar. 23, 2006
Applicants:

Ken-ichi Nonaka, Wako, JP;

Hideki Hashimoto, Wako, JP;

Seiichi Yokoyama, Wako, JP;

Kensuke Iwanaga, Wako, JP;

Yoshimitsu Saito, Wako, JP;

Hiroaki Iwakuro, Hanno, JP;

Masaaki Shimizu, Hanno, JP;

Yusuke Fukuda, Hanno, JP;

Koichi Nishikawa, Hanno, JP;

Yusuke Maeyama, Hanno, JP;

Inventors:

Ken-ichi Nonaka, Wako, JP;

Hideki Hashimoto, Wako, JP;

Seiichi Yokoyama, Wako, JP;

Kensuke Iwanaga, Wako, JP;

Yoshimitsu Saito, Wako, JP;

Hiroaki Iwakuro, Hanno, JP;

Masaaki Shimizu, Hanno, JP;

Yusuke Fukuda, Hanno, JP;

Koichi Nishikawa, Hanno, JP;

Yusuke Maeyama, Hanno, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/337 (2006.01); H01L 29/772 (2006.01); H01L 21/339 (2006.01); H01L 21/338 (2006.01); H01L 29/768 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.


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