The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2009

Filed:

Feb. 14, 2002
Applicants:

Milivoje Aleksic, Richmond Hill, CA;

Raymond M. LI, Markham, CA;

Danny H. M. Cheng, Scarborough, CA;

Carl K. Mizuyabu, Thornhill, CA;

Antonio Asaro, Scarborough, CA;

Inventors:

Milivoje Aleksic, Richmond Hill, CA;

Raymond M. Li, Markham, CA;

Danny H. M. Cheng, Scarborough, CA;

Carl K. Mizuyabu, Thornhill, CA;

Antonio Asaro, Scarborough, CA;

Assignee:

ATI Technologies ULC, Markham, Ontario, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01);
U.S. Cl.
CPC ...
Abstract

A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data.


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