The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2009
Filed:
May. 18, 2007
Harmander Singh, Austin, TX (US);
Alan J. Drake, Round Rock, TX (US);
Fadi H. Gebara, Austin, TX (US);
John P. Keane, Minneapolis, MN (US);
Jeremy D. Schaub, Austin, TX (US);
Robert M. Senger, Austin, TX (US);
Harmander Singh, Austin, TX (US);
Alan J. Drake, Round Rock, TX (US);
Fadi H. Gebara, Austin, TX (US);
John P. Keane, Minneapolis, MN (US);
Jeremy D. Schaub, Austin, TX (US);
Robert M. Senger, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.