The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2009
Filed:
Sep. 28, 2007
Prashant U. Kenkare, Austin, TX (US);
Andrew C. Russell, Austin, TX (US);
David R. Bearden, Austin, TX (US);
James D. Burnett, Austin, TX (US);
Troy L. Cooper, Austin, TX (US);
Shayan Zhang, Austin, TX (US);
Prashant U. Kenkare, Austin, TX (US);
Andrew C. Russell, Austin, TX (US);
David R. Bearden, Austin, TX (US);
James D. Burnett, Austin, TX (US);
Troy L. Cooper, Austin, TX (US);
Shayan Zhang, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line. The integrated circuit may further include a first power supply voltage terminal for receiving a first power supply voltage, wherein the first power supply voltage is provided to power the processor, and wherein the first power supply voltage is provided to power the plurality of memory cells during a first access operation of the plurality of memory cells. The integrated circuit may further include a second power supply voltage terminal for receiving a second power supply voltage higher than the first power supply voltage, wherein the second power supply voltage is provided to power the plurality of memory cells during a second access operation of the plurality of memory cells.