The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2009
Filed:
Nov. 02, 2006
Young-hee Song, Kyunggi-do, KR;
Il-heung Choi, Kyunggi-do, KR;
Jeong-jin Kim, Chungcheongnam-Do, KR;
Hae-jeong Sohn, Kyunggi-Do, KR;
Chung-woo Lee, Kyunggi-Do, KR;
Young-Hee Song, Kyunggi-do, KR;
Il-Heung Choi, Kyunggi-do, KR;
Jeong-Jin Kim, Chungcheongnam-Do, KR;
Hae-Jeong Sohn, Kyunggi-Do, KR;
Chung-Woo Lee, Kyunggi-Do, KR;
Samsung Electronics Co., Ltd., Gyeonggi-do, KR;
Abstract
A semiconductor chip has one or more peripheral bond pads. The semiconductor chip comprises a semiconductor substrate having a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on at least a part of the peripheral region of the semiconductor substrate. A passivation layer is formed on the bond pad-wiring pattern and exposed portions of the semiconductor substrate; a pad-rearrangement pattern disposed over the passivation layer and electrically connected to the bond pad-wiring pattern; and an insulating layer formed over the pad-rearrangement pattern. The insulating layer has an opening therein that exposes a portion of the pad-rearrangement pattern to define a bond pad. The bond pad is disposed over at least a part of the cell region.