The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 02, 2009
Filed:
Feb. 28, 2005
Fuja Shone, Hsinchu, TW;
Fuja Shone, Hsinchu, TW;
Skymedi Corporation, Taiwan, CN;
Abstract
A memory structure in a semiconductor substrate essentially comprises a first conductive line, two conductive blocks, two first dielectric spacers, a first dielectric layer, and a second conductive line. The first conductive line, e.g., a polysilicon line, is formed above the semiconductor substrate, and the two conductive blocks composed of polysilicon, for example, are formed at the two sides of the first conductive line and insulated from the first conductive line with the two first dielectric spacers. The first dielectric layer, such as an oxide/nitride/oxide (ONO) layer, is formed on the two second conductive blocks and above the first conductive line, and the second conductive line is formed on the first dielectric layer and is substantially perpendicular to the two doping regions. Accordingly, the stack of the conductive block, the first dielectric layer, and the second conductive line form a floating gate structure which can store charges. The first conductive line and conductive blocks function as a select gate and floating gates, respectively, whereas the doping regions and the second conductive line function as bit lines and a word line, respectively.