Iterative synthesis of an integrated circuit design for attaining power closure while maintaining existing design constraints

Abstract

An approach that iteratively synthesizes an integrated circuit design to attain power closure is described. In one embodiment, the integrated circuit design is initially synthesized to satisfy timing and power constraints. Results from the initial synthesis are fed back into the synthesis process where specific nodes in the circuit design are targeted to satisfy the timing and power constraints. Selected nodes in the circuit design are worked on in an iterative manner until it has been determined that all of selected nodes have undergone evaluation for satisfying timing and power constraints. Once all of the selected nodes have undergone evaluation for satisfying timing and power constraints, then a final netlist representing the circuit design is generated.