High speed hardware implementation of modified reed-solomon decoder

Abstract

A decoder suitable for use in a digital communications system utilizing an RS(n', k′) code modified from an RS(n, k) code receives n′-symbol vectors each including k′ message symbols and r′=n′−k′ parity symbols and decodes the n′-symbol vectors to correct errors therein, wherein n, k, n′, and k′ are integers, and k′<n′<n, k′<k<n, and wherein the decoder stores therein one erasure locator polynomial σ(x). The decoder includes a syndrome calculator for receiving the n′-symbol vectors and for calculating syndromes of each n′-symbol vector, wherein the i-th syndrome Sof one n′-symbol vector R′, (r, r, . . . , r), is S=R(α) for i=0, 1, . . . , n−k−1, wherein R(x)=rx+rx+ . . . +r, and means for finding the locations and values of the errors in each n′-symbol vector using the syndromes thereof and the one erasure locator polynomial σ(x).