The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2009

Filed:

Jun. 17, 2004
Applicants:

Jose DE Jesus Pineda DE Gyvez, Eindhoven, NL;

Alexander Guido Gronthoud, Eindhoven, NL;

Rachid Amine, Béni-Mellal, MA;

Inventors:

Jose De Jesus Pineda De Gyvez, Eindhoven, NL;

Alexander Guido Gronthoud, Eindhoven, NL;

Rachid Amine, Béni-Mellal, MA;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and apparatus for testing analogue or RF circuitry, wherein the power supply VDD is ramped up (step) and quiescent current measurements are taken at selected values of VDD (step) to generate a current signature (step). When the power supply is ramped up, all transistors in the circuit pass through several regions of operation, e.g. subthreshold (region A), linear (region B), and saturation (region C). The advantage of transition from region to region is that defects can be detected with distinct accuracy in each of the operating regions. Once the current signature has been generated it can be compared with the current signature of a fault-free device (step), to determine (step) if the device is operating correctly, and if not, it is discarded.


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