The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2009

Filed:

Jul. 31, 2007
Applicant:

James T. Walker, Palo Alto, CA (US);

Inventor:

James T. Walker, Palo Alto, CA (US);

Assignee:

Supertex, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/094 (2006.01);
U.S. Cl.
CPC ...
Abstract

A level translator has a pair of transistors, wherein a first transistor of the pair of transistors and a second transistor of the pair of transistors are complimentary. A pair of capacitors are provided, wherein a first capacitor of the pair of capacitors is coupled to a voltage input VIN and to a gate of a first transistor of the pair of complimentary transistors and a second capacitor of the pair of capacitors is coupled the voltage input VIN and to a gate of a second transistor of the pair of complimentary transistors. A flip flop device is provided having a first input coupled to a drain of the first transistor, and a second input coupled to a drain of the second transistor. A pair of resistors is provided, wherein a first resistor of the pair of resistors is coupled to the gate of the first transistor and to a voltage supply of VDD, and a second resistor of the pair of resistors is coupled to the gate of the second transistor and to a voltage supply VSS. A pair of clamping circuits is provided, wherein a first clamping circuit of the pair of clamping circuits is coupled to the gate of the first transistor and to a voltage supply of VDD, and a second clamping circuit of the pair of clamping circuits is coupled to the gate of the second transistor and to a voltage supply VSS.


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