Method of forming double gate transistors having varying gate dielectric thicknesses

Abstract

Double gate transistors () having different bottom gate dielectric thicknesses are formed on a first wafer () by forming a first gate dielectric layer (); removing part of the first gate dielectric layer () from a first area (); forming a second gate dielectric layer () to obtain a thinner bottom gate dielectric layer () over the first area () and a thicker bottom gate dielectric layer () over the second area (); and forming a planar bottom gate layer () over first and second gate dielectric layers. After inverting and bonding the first wafer () to a second wafer (), the bottom gate electrodes (--), bottom gate dielectric layers () and channel regions (--) for the first and second double gate transistors () are selectively etched prior to formation of the top gate structures.