The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2009

Filed:

Feb. 07, 2005
Applicants:

Young-ho Lee, Gyeonggi-do, KR;

Sun-yong Lee, Seoul, KR;

Doo-heun Baek, Gyeonggi-do, KR;

Tae-hoon Park, Seoul, KR;

Inventors:

Young-Ho Lee, Gyeonggi-do, KR;

Sun-Yong Lee, Seoul, KR;

Doo-Heun Baek, Gyeonggi-do, KR;

Tae-Hoon Park, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing an electronic device, which can obtain sufficient manufacturing margins and reduce a defect rate by compensating for a threshold voltage variation caused by the variation of a critical dimension (CD) of a gate electrode. An ion implanter controller and an ion implantation system perform the method. In the method, an ion implantation recipe for forming a junction contact plug of a transistor formed on the wafer is adjusted based on the measured CD. Then, ions are implanted into the wafer by using the adjusted ion implantation recipe. All defects that may occur in the transistor during previous manufacturing steps can be repaired after the transistor is formed, thus enhancing manufacturing margins.


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