The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2009
Filed:
May. 05, 2005
Jesse H. Jenkins, Iv, Danville, CA (US);
Frank C. Wirtz, Ii, Corrales, NM (US);
Roy D. Darling, Albuquerque, NM (US);
Thomas J. Davies, Jr., Albuquerque, NM (US);
Eric E. Edwards, Albuquerque, NM (US);
Jesse H. Jenkins, IV, Danville, CA (US);
Frank C. Wirtz, II, Corrales, NM (US);
Roy D. Darling, Albuquerque, NM (US);
Thomas J. Davies, Jr., Albuquerque, NM (US);
Eric E. Edwards, Albuquerque, NM (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Method and apparatus for providing secure programmable logic devices is described. One aspect of the invention relates to securing a programmable logic device having instruction register logic coupled to control logic via an instruction bus. A non-volatile memory is provided for storing at least one security bit for at least one instruction associated with the programmable logic device. Gating logic is provided in communication with the non-volatile memory and at least a portion of the instruction bus. The gating logic is configured to selectively gate decoded instructions transmitted from the instruction register logic towards the control logic based on state of the at least one security bit.