The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7535981 B1

PDF
Full Text
Expired
Date of Patent:
May. 19, 2009

Filed:

Nov. 17, 2005
Applicants:

Sohichi Tsukamoto, Gifu, JP;

Shuhsaku Matsuse, Kusatsu, JP;

Makoto Ueda, Kyoto-fu, JP;

Inventors:

Sohichi Tsukamoto, Gifu, JP;

Shuhsaku Matsuse, Kusatsu, JP;

Makoto Ueda, Kyoto-fu, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention generates an output clock signal CLKreq having a frequency freq between the frequency fref/A of a divided clock signal CKLand the frequency fref/(A+1) of a divided clock signal CLK. A clock divider circuit selectively generates divided clock signals CLK, CLK. A discrete value correction circuit controls the clock divider circuit so as to repeat C times the process of generating the clock signal CLKonce and the clock signal CLK(Q−1) times and then to generate the clock signal CLKR times if C<D and so as to repeat D times the process of generating the clock signal CLKonce and the clock signal CLK(Q−1) times and then to generate the clock signal CLKR times if C>D. A, B, and C are natural numbers satisfying freq=fref/(A+C/B). In D=B−C, Q is a quotient of B/C if C<D or a quotient of B/D if C>D.


Find Patent Forward Citations

Tsukamoto, Sohichi. (2009). Clock generation circuit and method thereof (U.S. Patent No. 7535981). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7535981

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