The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 19, 2009

Filed:

Jul. 26, 2006
Applicants:

Fumio Yuuki, Fujimino, JP;

Hiroki Yamashita, Hachioji, JP;

Inventors:

Fumio Yuuki, Fujimino, JP;

Hiroki Yamashita, Hachioji, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/20 (2006.01); H03K 19/094 (2006.01); H03K 17/16 (2006.01); H03K 19/003 (2006.01); H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
Abstract

A first current source generating a current I+I when a control signal is in 'H' level and a current Iwhen it is in 'L' level, a current mirror circuit transferring a current generated in the first current source and composed of first and second MOS transistors, and a second current source connected to the second transistor and generating I+I are provided. Further, a node branched from a connection node between the second transistor and the second current source is formed, and a logic unit including a flip-flop circuit formed of a differential amplifier is driven through the node. The logic unit is in an active state when the control signal is in ‘H’ level and it is in an inactive state when the signal is in ‘L’ level. When the logic unit is in an active state, it processes a data input signal to generate data output signal.


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