The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2009
Filed:
Oct. 12, 2005
Peter C. Salmon, Mountain View, CA (US);
Peter C. Salmon, Mountain View, CA (US);
Salmon Technologies, LLC, Mountain View, CA (US);
Abstract
A method is described for combining the diverse strengths of two materials in a tiled film construction. The first material provides a foundation of intersecting grid lines on a substrate and the second material is contained within the grid lines and has a valued property for a particular application. In a preferred embodiment, a tiled dielectric layer has improved low-k dielectric performance while avoiding film stress problems that can lead to delamination or cracking. CTE mismatch is overcome at the cost of an additional masking step. This tiling method and layered binary construction enable Cytop to be used as a high performance low-k dielectric on most substrates including semiconductor wafers and copper panels or foils.