The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2009
Filed:
Sep. 28, 2007
Ryuichi Kanamura, Tokyo, JP;
Ryuichi Kanamura, Tokyo, JP;
Sony Corporation, Tokyo, JP;
Abstract
A process for production of a semiconductor device having a multi-layer wiring of dual damascene structure in a low-dielectric constant interlayer insulating film. The process consists of the following steps. A first insulating film and a second insulating film are formed. A first to third mask forming layers are formed. The third mask forming layer is patterned so as to form the third mask for the wiring groove pattern. A resist mask of the connecting hole pattern is formed on the second mask forming layer including the third mask. The third mask and the second and first mask forming layers are etched, and the second insulating film is etched. The second mask of the wiring groove pattern is formed by using the third mask, and the connecting hole is made to the middle of the first insulating film. The first mask forming layer is etched by using the second mask, and the first mask of the wiring groove pattern is formed, and the first insulating film remaining at the bottom of the connecting hole is etched so as to make the connecting hole. The wiring groove is formed in the second insulating film by using the first or second mask.