The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 19, 2009
Filed:
Dec. 07, 2006
Bruce Michaud, Clayton, CA (US);
Peter Ammann, San Jose, CA (US);
George Sorenson, Fremont, CA (US);
Bruce Michaud, Clayton, CA (US);
Peter Ammann, San Jose, CA (US);
George Sorenson, Fremont, CA (US);
nVidia Corporation, Santa Clara, CA (US);
Abstract
Embodiments of methods and apparatus for plating a PCI Express edge connector are described. In one embodiment, a printed circuit board having connectors is employed for electroplating one or more of the connectors formed thereon. The printed circuit board comprises a substrate having one or more layers, and a plurality of connectors formed on one or more of the layers, wherein at least one connector includes at least one short pin and at least one extra pin. The at least one extra pin extends beyond an outer shape of the printed circuit board after fabrication. The printed circuit board also includes connection circuitry formed on one or more of the layers, wherein the connection circuitry is configured to electrically connect the short pin with the extra pin at least during electroplating of said short pin.