The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 12, 2009
Filed:
Apr. 09, 2007
Applicant:
Isao Naritake, Kanagawa, JP;
Inventor:
Isao Naritake, Kanagawa, JP;
Assignee:
NEC Electronics Corporation, Kanagawa, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/10 (2006.01);
U.S. Cl.
CPC ...
Abstract
A semiconductor integrated circuit device includes: a first bias generating circuit, a second bias generating circuit and a control circuit. The first bias generating circuit generates a first substrate bias voltage of a P-channel transistor. The second bias generating circuit generates a second substrate bias voltage of N-channel transistor. The control circuit controls the first bias generating circuit and the second bias generating circuit independently on the basis of operating states of circuits to which the first substrate bias voltage and the second substrate bias voltage are applied.