The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2009
Filed:
May. 18, 2006
Gregor Nixon, High Wycombe, GB;
Mark Jervis, High Wycombe, GB;
Zhengjun Pan, High Wycombe, GB;
Gihan DE Silva, High Wycombe, GB;
Steven Perry, High Wycombe, GB;
Gregor Nixon, High Wycombe, GB;
Mark Jervis, High Wycombe, GB;
Zhengjun Pan, High Wycombe, GB;
Gihan De Silva, High Wycombe, GB;
Steven Perry, High Wycombe, GB;
Altera Corporation, San Jose, CA (US);
Abstract
While debugging, a user chooses an incremental recompile. Internal signals of interest are selected and output pins are optionally reserved. An incremental recompile of the compiled design includes compiling a routing from each internal signal to an output pin. The technology-mapped netlist and placing and routing information corresponding to an original compiled design are saved into a database during full compilation. During debugging, an incremental compiler retrieves this information to build the original routing netlist. The database building, logic synthesis and technology mapping stages may be skipped. New connections are added, fitted to the device, and then the final routing netlist is output into a programming output file (POF) in a form suitable for programming the PLD. The user views the internal signals at the output pins chosen. The user may iterate through this process many times in order to debug the PLD. The debugging assignments may be deleted.