The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2009
Filed:
Mar. 15, 2007
Hiroyuki Sadakata, Osaka, JP;
Hiroyuki Sadakata, Osaka, JP;
Panasonic Corporation, Osaka, JP;
Abstract
A semiconductor memory device of the present invention provides, in a memory having an hierarchical bit line structure, a test mode which causes all switches for selecting hierarchical bit lines and a main bit line in an activated memory array to be connected all the time. With this configuration, it is possible to perform a disturb refresh test on a memory cell arrays basis regardless of the hierarchical bit line structure. Possibility of an erroneous read-out, which may be caused by connecting each of the hierarchical bit lines to one another and a consequent increase in a bit line load capacity, may be prevented by providing a timing control such that the switches are connected after a normal mode operation.