The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2009
Filed:
Dec. 30, 2005
Sung-dong Kim, Seongnam-si, KR;
Eun-sik Kim, Seoul, KR;
Ju-hwan Jung, Seoul, KR;
Hyoung-soo Ko, Seoul, KR;
Dong-ki Min, Seoul, KR;
Hong-sik Park, Seoul, KR;
Seung-bum Hong, Seongnam-si, KR;
Sung-dong Kim, Seongnam-si, KR;
Eun-sik Kim, Seoul, KR;
Ju-hwan Jung, Seoul, KR;
Hyoung-soo Ko, Seoul, KR;
Dong-ki Min, Seoul, KR;
Hong-sik Park, Seoul, KR;
Seung-bum Hong, Seongnam-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, KR;
Abstract
A magnetic logic device (MLD) and methods of manufacturing and operating an MLD are provided. The MLD includes: a first interconnection; a lower magnetic layer formed on the first interconnection, the lower magnetic layer having a magnetization direction fixed in a predetermined direction; a non-magnetic layer formed on the lower magnetic layer; an upper magnetic layer formed on the non-magnetic layer, the upper magnetic layer having a magnetization direction parallel or anti-parallel to the magnetization direction of the lower magnetic layer; and a second interconnection formed on the upper magnetic layer. A first current source is disposed between one end of the first interconnection and one end of the second interconnection and a second current source is disposed between the other end of the first interconnection and the other end of the second interconnection.