The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2009
Filed:
Mar. 11, 2005
Dipankar Bhattacharya, Macungie, PA (US);
John Kriz, Palmerton, PA (US);
Che Coi Leung, Bethlehem Township, Northhampton County, PA (US);
Duane J. Loeper, Spring City, PA (US);
Yehuda Smooha, Allentown, PA (US);
Dipankar Bhattacharya, Macungie, PA (US);
John Kriz, Palmerton, PA (US);
Che Coi Leung, Bethlehem Township, Northhampton County, PA (US);
Duane J. Loeper, Spring City, PA (US);
Yehuda Smooha, Allentown, PA (US);
Agere Systems Inc., Allentown, PA (US);
Abstract
An ESD clamp circuit for use between separate power rails. An ESD clamp is based on a wide nMOSFET. A symmetrical circuit is designed vis-à-vis the two power rails, with respect to ground, allowing discharge of an ESD surge in both polarities of stress. An nMOSFET device drives the gate of a large nMOSFET (e.g., having a device width between 1000 and 10,000 microns). The large power rail-to-power rail nMOSFET has its gate controlled by the output inverter stage of either ESD detection circuit connected to a respective power supply rail. The gate is switched to a common ground during normal operation of the integrated circuit.