The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2009
Filed:
Feb. 07, 2007
Cheng-hung Huang, Taipei, TW;
Hsien-chieh Lin, Taoyuan County, TW;
Kuo-chun Chiang, Taoyuan, TW;
Shing-fun Ho, Taipei, TW;
Cheng-Hung Huang, Taipei, TW;
Hsien-Chieh Lin, Taoyuan County, TW;
Kuo-Chun Chiang, Taoyuan, TW;
Shing-Fun Ho, Taipei, TW;
Nan Ya Printed Circuit Board Corporation, Lunchu, Taoyuan, TW;
Abstract
A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second metal foil and the dielectric interposer with a portion of the first metal foil as its bottom. A die is mounted within the recessed cavity and makes thermal contact with the first metal foil. A build-up material layer covers the second metal foil and an active surface of the die. The build-up material layer also fills the gap between the die and the dielectric interposer. At least one interconnection layer is provided on the build-up material layer and is electrically connected with a bonding pad disposed on the active surface of the die via a plated through hole.