The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2009
Filed:
Mar. 02, 2007
Hiroaki Ueno, Ibaraki, JP;
Tetsuzo Ueda, Toyonaka, JP;
Yasuhiro Uemoto, Otsu, JP;
Daisuke Ueda, Ibaraki, JP;
Tsuyoshi Tanaka, Neyagawa, JP;
Manabu Yanagihara, Toyonaka, JP;
Yutaka Hirose, Nagaokakyo, JP;
Masahiro Hikita, Ashiya, JP;
Hiroaki Ueno, Ibaraki, JP;
Tetsuzo Ueda, Toyonaka, JP;
Yasuhiro Uemoto, Otsu, JP;
Daisuke Ueda, Ibaraki, JP;
Tsuyoshi Tanaka, Neyagawa, JP;
Manabu Yanagihara, Toyonaka, JP;
Yutaka Hirose, Nagaokakyo, JP;
Masahiro Hikita, Ashiya, JP;
Panasonic Corporation, Osaka, JP;
Abstract
It is an object of the present invention to provide a semiconductor device, which can simultaneously achieve a normally-off mode of HFET and an improvement in I, and further achieve an improvement in gand a reduction in gate leakage current. In order to keep a thin barrier layeron an operation layerof a substratedirectly under a gate electrode for mostly contributing to achieve the normally-off mode and also implement the high I, it is configured in such a way that a thickness of the barrier layercan be increased by the semiconductor layerbetween gate and source regions and between gate and drain regions. It is therefore possible to achieve the normally-off mode and an improvement in Ias compared with an FET in which a thickness of the barrier layer is designed so as to be uniform. An insulating filmwith a dielectric constant higher than that of the barrier layer is further inserted between a gate electrodeand the barrier layers, so that an improvement in gand a reduction in gate leakage current can be achieved.