The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7526399 B1

Expired

Date of Patent:

Apr. 28, 2009

Filed:

Sep. 01, 2004

Method of delay calculation in integrated circuit, and timing analysis system using the same

Applicants:

Junko Matsumoto, Kanagawa, JP;

Tetsuya Akimoto, Kanagawa, JP;

Inventors:

Junko Matsumoto, Kanagawa, JP;

Tetsuya Akimoto, Kanagawa, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:

Foley & Lardner LLP

Primary Examiner:

Manuel L Barbee

Int. Cl.

CPC ...

G06F 9/45 (2006.01);

U.S. Cl.

CPC ...

Abstract

In a method of delay calculation of relative timing paths of an integrated circuit, each of the paths contains at least one stage. The method is achieved by calculating an on-chip variation depending on a systematic component and an on-chip variation depending on a random component; and by carrying out delay calculation of relative timing paths by using the on-chip variation depending on the systematic component and the on-chip variation depending on the random component.

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Matsumoto, Junko. (2009). Method of delay calculation in integrated circuit, and timing analysis system using the same (U.S. Patent No. 7526399). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7526399

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