The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 28, 2009
Filed:
Jul. 13, 2006
Sung-jun Kim, Hwaseong-si, KR;
Chang-ki Hong, Seongnam-si, KR;
Bo-un Yoon, Seoul, KR;
Jae-kwang Choi, Suwon-si, KR;
Sung-jun Kim, Hwaseong-si, KR;
Chang-ki Hong, Seongnam-si, KR;
Bo-un Yoon, Seoul, KR;
Jae-kwang Choi, Suwon-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
A method for manufacturing a multi-level transistor on a substrate. The method includes forming a first transistor on a first active region, forming a first selective epitaxial growth (SEG) layer on the substrate, and forming a preliminary second SEG layer and a dummy layer, wherein the preliminary second SEG layer is formed directly on only the first SEG layer and a portion of the first insulating layer formed on the cell region of the substrate, and wherein the dummy layer is formed on the peripheral region of the substrate. The method further includes planarizing the preliminary second SEG layer using the dummy layer as a stop layer to form a second SEG layer, forming a second active region from the second SEG layer formed on a first insulating layer, and forming a second transistor on the second active region.