The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2009
Filed:
Feb. 18, 2005
Armen Kroyan, San Francisco, CA (US);
Youping Zhang, Fremont, CA (US);
Etsuya Morita, Dublin, CA (US);
Adrianus Ligtenberg, Los Altos Hills, CA (US);
Armen Kroyan, San Francisco, CA (US);
Youping Zhang, Fremont, CA (US);
Etsuya Morita, Dublin, CA (US);
Adrianus Ligtenberg, Los Altos Hills, CA (US);
Takumi Technology Corporation, Santa Clara, CA (US);
Abstract
A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into a desired level of granularity based on specified layout and integrated circuit properties. At that localized level, the design rules are adjusted appropriately to capture the critical aspects from a manufacturability standpoint. These adjusted design rules are then used to perform localized layout manipulation and mask data conversion.