The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2009
Filed:
Dec. 19, 2005
Alfredo Aldereguia, Cary, NC (US);
Marcus Alan Baker, Apex, NC (US);
Justin Potok Bandholz, Cary, NC (US);
Jeffrey Buchanan Williams, Raleigh, NC (US);
Alfredo Aldereguia, Cary, NC (US);
Marcus Alan Baker, Apex, NC (US);
Justin Potok Bandholz, Cary, NC (US);
Jeffrey Buchanan Williams, Raleigh, NC (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A receiving processor is configured with a normal (operational) path and a test path. The test path is configured in parallel with the normal path. The test path simulates and receives as input the same data as the normal path, but the test path has a separate voltage reference (V) which is applied to a test input buffer. The same data input to normal buffer is also input to the test buffer. The output of the test buffer is input to a test latch. A clocking signal supplied to the test latch is a variable clocking signal enabling the clock signal to be skewed selectively. The output of the test latch is compared with the output of the normal latch, and differences between the two output signals defines an error for a particular voltage/clock-skew combination.