The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2009

Filed:

Jul. 26, 2005
Applicants:

William A. Holder, Vestal, NY (US);

Damian L. Osisek, Vestal, NY (US);

Thomas M. Vail, Owego, NY (US);

Donald P. Wilton, Vestal, NY (US);

Inventors:

William A. Holder, Vestal, NY (US);

Damian L. Osisek, Vestal, NY (US);

Thomas M. Vail, Owego, NY (US);

Donald P. Wilton, Vestal, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Aliasing errors, occasioned by, for example, a programming error resulting in including extra or missing bits in a storage address, wrong addressing mode, or wrong address context, are detected by providing a storage address configuration including gaps in valid addresses. Such a programming error is detected and an exception is thrown (that is, an addressing error is detected and indicated) responsive to an address reference to such a gap in valid addresses. Gaps are configured at complementary address ranges to facilitate detection of such aliasing errors.


Find Patent Forward Citations

Holder, William. (2009). System and method for testing for memory address aliasing errors (U.S. Patent No. 7523291). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7523291

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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