The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2009

Filed:

Jan. 04, 2006
Applicants:

Fouad Kiamilev, Newark, DE (US);

Joshua Kramer, Newark, DE (US);

Yongrong Zuo, Newark, DE (US);

Inventors:

Fouad Kiamilev, Newark, DE (US);

Joshua Kramer, Newark, DE (US);

Yongrong Zuo, Newark, DE (US);

Assignee:

University of Delaware, Newark, DE (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 3/00 (2006.01); H04L 25/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus and method for an interface for transmitting high speed data between circuits. A driver circuit produces first and second differential currents from a digital signal that drive first and second transmission lines. A receiver is connected through first and second terminating resistors to said transmission lines. The resistive elements are in turn connected to first and second common base amplifiers where the differential currents are converted to a differential voltage. The input impedance to the first and second common-base amplifiers is further lowered by a differential amplifier having inputs connected to the inputs of the common-base amplifiers, and an output connected to the bases of said common-base amplifiers. As a result, voltage conversion of the differential signals takes place in the common-base amplifiers and not in the terminating resistors, reducing the level of the differential currents and permitting an increase in the digital data rate. In addition, a common-gate amplifier configuration of the present invention is provided as well as a method for dynamically determining an optimal transmit power level for the driver circuit and for performing an accelerated bit error rate measurement.


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