The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2009
Filed:
Dec. 26, 2006
Sumantra Seth, Karnataka, IN;
Somasunder Kattepura Sreenath, Karnataka, IN;
Sumantra Seth, Karnataka, IN;
Somasunder Kattepura Sreenath, Karnataka, IN;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A biasing circuit is presented. The biasing circuit includes a primary biasing circuit, a replica circuit and an amplifier. The primary circuit provides a biasing voltage and a primary voltage. The biasing voltage is the output of the biasing circuit. The replica biasing circuit provides a replica voltage. The replica biasing circuit includes a first resistive element said first resistive element having a resistive characteristics; a first current source said first current source having the first resistive element for generating a current as a function of the first resistive element; a first node to couple to receive the first current source to generate the replica voltage at the first node; a second current source; a second node to coupled to receive the second current source, and a second resistive element coupled between the first noted and the second node, said second resistive element having substantially similar resistive characteristics to that of the first resistive element. The amplifier having a first input terminal to couple to receive the primary voltage from the primary biasing circuit, a second input terminal to couple to receive the replica voltage from the replica biasing circuit, and an output terminal to couple to the primary biasing circuit to adaptively adjust a current through the primary biasing circuit according to the received voltages. Further, a current mirror circuit is provided having the biasing circuit.