The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2009

Filed:

Jan. 03, 2007
Applicants:

Deok-kee Kim, Bedford Hills, NY (US);

Seong-dong Kim, LaGrangeville, NY (US);

Oh-jung Kwon, Hopewell Junction, NY (US);

Inventors:

Deok-kee Kim, Bedford Hills, NY (US);

Seong-Dong Kim, LaGrangeville, NY (US);

Oh-Jung Kwon, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2006.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01); H01L 31/00 (2006.01); H01L 29/00 (2006.01); H01L 23/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region includes a PFET; and, the second transistor region includes an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each include a compressive region, a compressive liner, a tensile region, and a tensile liner.


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