The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2009
Filed:
Mar. 23, 2007
Tiesheng LI, San Jose, CA (US);
Yu Wang, Fremont, CA (US);
Yingying Lou, Shanghai, CN;
Anup Bhalla, Santa Clara, CA (US);
Tiesheng Li, San Jose, CA (US);
Yu Wang, Fremont, CA (US);
Yingying Lou, Shanghai, CN;
Anup Bhalla, Santa Clara, CA (US);
Alpha & Omega Semiconductor, Ltd, Hamilton, BM;
Abstract
A method for determining the depth etch, a method of forming a shielded gate trench (SGT) structure and a semiconductor device wafer are disclosed. A material layer is formed over part of a substrate having a trench. The material fills the trench. A resist mask is placed over a test portion of the material layer thereby defining a test structure that lies underneath the resist mask. The resist mask does not cover the trench. The material is isotropically etched and a signal related to a resistance change of the test structure is measured. A lateral undercut Dof the test structure is determined from the signal and an etch depth Dis determined from D. The wafer may comprise one or more test structures forming a bridge circuit; one or more metal contacts that electrically connect the test structures through contact holes: and resist layer including over the test structures.