The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2009

Filed:

Nov. 30, 2007
Applicants:

Akio Kaneko, Yokohama, JP;

Motoyuki Sato, Tsukuba, JP;

Katsuyuki Sekine, Yokohama, JP;

Tomohiro Saito, Yokohama, JP;

Kazuaki Nakajima, Tokyo, JP;

Tomonori Aoyama, Yokohama, JP;

Inventors:

Akio Kaneko, Yokohama, JP;

Motoyuki Sato, Tsukuba, JP;

Katsuyuki Sekine, Yokohama, JP;

Tomohiro Saito, Yokohama, JP;

Kazuaki Nakajima, Tokyo, JP;

Tomonori Aoyama, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device having a MOSFET of a first conductivity type and a MOSFET of a second conductivity type different from the first conductivity type formed on a semiconductor substrate, the method has: forming a gate insulating film; forming a first gate electrode layer, and forming a second gate electrode layer; forming a first metal containing layer on said first gate electrode layer and said second gate electrode layer; forming a second metal containing layer for preventing diffusion of a metal on said first metal containing layer; forming a third metal containing layer on said second gate electrode layer from which said first metal containing layer and said second metal containing layer are selectively removed, the third metal containing layer having a thickness different from the thickness of said first metal containing layer in a case where the third metal containing layer contains the same metal or alloy as the metal or alloy contained in said first metal containing layer; and performing a thermal processing, thereby causing reaction between the metal contained in said first metal containing layer and said first gate electrode layer to convert said first gate electrode layer into an alloy and causing reaction between the metal contained in said third metal containing layer and said second gate electrode layer to convert said second gate electrode layer into an alloy, thereby forming gate electrodes of different compositions.


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