Wiring methods to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle-time overlap violations

Abstract

Wiring structures and methods for integrated circuit designs which are adapted to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle time overlap violations in launch/capture clocking systems are provided, whereby the A/B/C (test/launch/capture) clock wire nets are designed using a five parallel track wire segment, in which the B clock wire is represented as a double track with one metal track and one adjacent isolation/shielding track, the C clock wire is represented as a double track with one metal track and one adjacent isolation/shielding track, and where the A test clock wire is represented as a single track comprising test signal wire disposed between the B and C signal wires.