The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2009

Filed:

Jul. 18, 2006
Applicants:

Shawn Scouten, Kanata, CA;

Colin Cramm, Kanata, CA;

Malcolm Stevens, North Gower, CA;

Kenji Suzuki, Kanata, CA;

Brian Wall, Stittsville, CA;

Med Belhadj, Ottawa, CA;

Inventors:

Shawn Scouten, Kanata, CA;

Colin Cramm, Kanata, CA;

Malcolm Stevens, North Gower, CA;

Kenji Suzuki, Kanata, CA;

Brian Wall, Stittsville, CA;

Med Belhadj, Ottawa, CA;

Assignee:

Cortina Systems, Inc., Sunnyvale, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/42 (2006.01); G06F 12/00 (2006.01); H03L 7/06 (2006.01); H03K 5/01 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.


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